1. Field of the Invention
The present invention relates to an impedance-matched supply circuit for supplying a two-wire line and to a multi-channel supply circuit, in particular for supplying power to subscriber devices in telecommunications networks.
2. Description of the Prior Art
Typical telephone networks are generally constructed from two-wire lines which serve both to supply power to connected terminals and to transmit signals. Even relatively recent ISDN systems need power to be supplied at the exchange end in order to operate the network terminations at the subscriber end. The supply voltage applied to a two-wire line is usually 100 volts, this voltage and the resultant current being supplied by the exchange.
When supplying power, particular requirements are imposed on maximum currents and the symmetry of the two lines forming the two-wire line. In order to satisfy all of the technical requirements, the relevant supply circuits must limit the current which is injected into the corresponding subscriber loop.
A circuit which is typically used to supply power is illustrated in FIG. 3.
FIG. 3 illustrates a circuit arrangement IPC for supplying a two-wire subscriber line TL in accordance with the prior art. In this case, a first line connection OUT1′ of the two-wire line TL is coupled to earth GND via a first resistor R1. A second two-wire line connection OUT2′ is connected to a supply voltage potential VBAT via the controllable path D-S of a transistor T1 and via a second resistor R4. The transistor T1 has a source, a drain, a bulk and a gate connection G, S, B, D, the drain connection D being connected to the second two-wire line connection OUT2′ and the bulk and source connections B, S being connected to the second resistor R4. Provision is also made of an operational amplifier (OP1) which has two inputs E1, E2 and an output A. The output A is connected to the gate connection G of the transistor T1. A setting potential VR1 is supplied to the first input E1, and the second input E2 is connected to a circuit node K between the source connection S of the transistor T1 and the second resistor R4.
In general, the first and second resistors R1, R4, the transistor T1 and the operational amplifier OP1 are integrated, and the actual two-wire line TL is connected to the supply circuit IPC via a respective resistor R2, R3. In the case of ISDN applications, the current intensity which is injected into the subscriber loop TL must be limited to approximately 50 mA. This is effected, in the case of the circuit IPC in accordance with the prior art, by controlling the channel resistance of the transistor T1 by applying a control voltage to the gate connection G of the latter. In this case, said control voltage is provided by the operational amplifier OP1 which receives the voltage dropped across the controllable path D-S of the transistor T1 at the line node K as an input signal and compares it with a setting potential VR1.
In the case of telephone line networks, in particular, a particular requirement is additionally imposed on the symmetry of the currents which are present. By way of example, it is necessary for the impedance between earth GND and the positive first line connection OUT1 of the subscriber line to be equal to the impedance between the second line connection OUT2 of the subscriber line and the second supply voltage potential VBAT.
In the case of telephone networks, the second supply voltage potential is generally −100 volts. In the case of ISDN, the two impedances connected to the respective two-wire line must amount to an absolute value of, as precisely as possible, 28 Ω. In this case, the tolerance must not be more than 0.4 Ω in accordance with the system requirements. In the case of a circuit in accordance with the prior art, the symmetry in the corresponding impedances can only be achieved if, in particular, the channel resistance of the transistor T1 is only approximately 1 Ω since the temperature dependence of the channel resistance and manufacturing tolerances prevent the precise symmetry required in the case of relatively high resistance values for the controllable path.
On account of this requisite low resistance of only 1 106 in this example, a circuit arrangement in accordance with the prior art occupies a very large chip area. The comparatively large dimensions of the transistor T1 having a low resistance also lead to a high capacitance between the gate and drain or source. As a result, the current is limited relatively sluggishly. The disadvantages of such a basic circuit in accordance with the prior art thus reside, in particular, in the sluggish current-limiting behaviour and in the considerable outlay in terms of area in order to achieve the tolerances required in the symmetry of the impedances.